The Rewrite Rule Machine (RRM) is a massively parallel machine being developed at SRI International that cambines the power of SIMD with the general grain an d coarse-grain paralleslism, and is based on and portin gparallel programs. In particular, the RRM can be programmed very naturally with very high-level declarative langauges featuring implicit parallelism. This paper gives on overview of the RRM's architecture and discusses performance estimates based on very detailed register-level simulations at the chip level together with more abstract simulatins and modeling for higher levels