Time warp has evolved to common technique for distributed simulation. Speedup in time warp simuation systems mainly dependens on two overhead factors: first, the load on the simulators has to be sell balanced and second, communication and rollbacks have to be kept to a minimum both of these factors are influenced by the partitioning of the simulated system. In this paper, we focus on varions static paritioning schemes used partition digital circuits for distributed simulation. A new hierarchical partitioning approach is presneted , compared and rated with other partitioning schemes by evaluating benchmark cicruits . Partitioning is done in two steps: a fine grainded culstering step based on corollas and a coarse grained clustering step based on corollas and coarse grained step forming partitions using the connectivity matrix. The corolla approach yields very good partitioning results even for a large number of partitions. the achieved speedups are almost linear (up to 12 partitions for large circuits), as long as the partition sizes are large enough so that communication between the simulators is not a bottleneck. The results reveal the great impact of partitioning on the acceleration of distributed logic simulation and show the effectiveness of the presented corolla partitioning scheme