In this paper we presnt two hardware components for high performance parallel computing; a superscalar RISC microprocessor with an integrated 400 megabytes/sec user-level network interface (the 88110MP), and a compoanion 8x8 ;pw-latency packet router chip (ARCTIC). The design point compines very low message overhead and high deivered communicatins bandwidth with a commercially competitive sequential processor core. The network interface is directly programmed in user mode as an intruction set extendison tto eht mototora 88100. Importantly, naming and protection mechanisms are provided to support robust multi-user space and time sharing. Thus, finegrain messaging and synchronization can be supported efficiently, without compromising per-rprocessor performance or system intgrity. Perliminary performance modeling rsluts are presnted