In data communication via internet, security is becoming one of the most influential aspects. One way to support it is by classifying and filtering ethernet packets within network devices. Packet classifications is a fundamental task for network devices such as routers,firewalls,and intrusion detection systems. In this paper we present archhitecture of fast and recnfigurable Packet Classification Engine(PCE). This engine is used in FPGA-based firewall. Our PCE inspeets multi-dimensional field of packet header sequentially basedon tree-based algorithm. This algorithm simplifes overall system to a lower scale and leads to a more secure system. The PCE based on Source IP Address, Destination IP Address, Source Port, Destination Port, and Protocol fields of the packet header. These are basic fields to know wheher it is a dangerous or normal packet before inspecting the content. Using implementation of tree-based algorithm in the architecture, firewall rules are rebuilt into 24-bit sub-rules which are read as processor instruction in the inspection process. The inspection process is comparing one sub-rule with input field of header every clock eycle.The propesed PCE shows 91 MHz clock frequency in Cyclone II EP2C70F89C6 with 13 clocks throughtput average from input to output generation. The use of tree-based algorithm simplifies the mulidimensional packet inspection and gives us reconfigurable as well as scable system. The architecture is fast,reliable ,and adaptable and also can maximize the advantages of the algorithm very well. Although the PCE has high frequency and little amount of clock,filtering speed of a firewall also depends on the other components,such as packet FIFO buffer. Fast and reliable FIFO buffer is needed to supprt the PCE. This PCE also is not completed wth rule update mechanism yet. This proposed PCE is tasted a compenet of FPGA-based firewall to filter Ethernet packet with FPGA DE2 Board using NIOS II platform.