In the push for ever increasing performance out of processor architectures, there is a need to expand beyond the limitatins of existing scalar approaches. Supercalar architectures provide one such means. By dinamically executing more than one instruction tper clock cycle, superscalar architectures can improce performance without relying solely on technology improvements for superscalar control implementatin, called the schedule table. The schedule table facilitates dependency checking, out of order instruction issue, out pf order execution, brach prediction, speculative execution, precise interrupts, and fast and efficient misprediction recovery