A recurrent problm posed by parallel processing architectures is that of communication latency. In this work, the latency problem is presented with special emphasis given to RISC based multiprocessors . An interprocessor communication model for parallel progrms based on localiry is presented. This model enable the programmer to manipulate locality at the language level and to take advantage of currently available system hardware to reduce latency. Further, a hardware node architecture for a latency-tolerant RISC.