An approach for high performance parallel logic simulation on a local area network on workstation computers in discussed is discusse in this paper. The single, shared transmission medium often found in such networks plasces limitations on parallel execution, hence a reduction i the frequency of synchronization is purued by combining a circuit partitioning methodology with a specific synchronization constraint. A consequence of the partitioning methodology is replication of objects between blocks of a partition. A Partitioning procedure based on iterative improvement is discribed for reducing replication while prserving load banace. Two interprocessor synchronization. Experiments conducted on three large sequential circuits indicate that reasonable speedup is achievable for well-ballanced partitions, and that optimistic synchronization provides a modest improvement in performance over conservative synchronization.