As multi-core architectures scale in size, on-chip networks (NoC) have become the main communication architecture, replacing dedicated interconnections and shared buses. NoC architectures have to deliver good latency-throughtput performance in the face of very tight power and are budgets. live power measurement is neccessary for both hardware and software designer, but is requires too much time for simulation, especially for embedded systems. the major constribution of this paper is to present a simple method for rapidly estimating power consumption and find the hotspots in the network-on-chip(NoC) at two different resolutions. in addition to the low-level cyscle-accurate simulation, we also build a hight-level NoC simulation platfrom for multi-core SoCs, called TLM-OVT level. the platform, implemented by systemC, allows early exploration of the performance and power consumption of NoC, which is able to handle arbitrary topologies and routing schemes. in the the experiments, we compare the implemented high-level simulation platform with cycle-accurate simulator. the result show that the TLM-PVT simulator gives a high simulation speedup factor with a negligible performance estimationn error margin.