SIMD instruction cache (or I-cache) is proposed to remedy a heretofore un-compensated instruction delivery rate limita- tion of SIMD computers. This paper introduces the concept of SIMD I-cache and sketches the I-cache design space. On the basis of throughput using chip area as a hardware cost constraint, detailed evaluations of simple I-cache variants for a diverse set of sample problems are presented. Sim- ple I-cache variants occupy negligible area in chips while providing significant speedups, even for problems ordinar- ily thought to be inherently communication-bound. These results suggest that I-cached SIMD computers exhibit the highest throughput of any multiprocessors for scalable data- parallel problems.