Ordered binary decision diagrams (OBDD) have found extensive use in various algorithms for analyzing Boolean functions. it is known that the size of OBDD is sensitive to the variable ordering used while building such binary decision diagrams (BDD). the size of the representation may vary from linear to exponential. n particular, BDD sizer are very sensitive to the order chosen on input variables. the size themselves depend on the variable order used thus, these are a need to find a variable order that minimize the number of nodes in a BDD. in this paper we find out the best variable ordering for OBDDs using gate level combinational circuits. Boolean functions at different primary outputs are represented in terms of primary input variables using the same variable ordering. in all examples, the ordering generates smaller OBDDs than the other previously proposed heuristics. the objective is to provide a fast way to generate OBDs of reasonable sizes and the results could be used as a good initial solution to any semi-exhaustive ordering method to further reduce the sizes [4,5]